welcome to lecture number 119 in digital electronics course in the last presentation I explained you basics of sequential circuits and I explained you that the only difference between the combinational circuits and the sequential circuits is the memory block in sequential circuits we have memory element and it is used to store the past output so what we want we want to store a single bit number we want to store 0 or 1 and if we can store 0 or 1 we can definitely store multi bit number like 1 0 0 101 etc so what Prime aim
is to store 0 or 1 a single bit and for this purpose we will use this circuit and we call it as a latch the basic storage element is called latch and we will study SR latch in this presentation it is of two types the first one is the nor SR latch that you can see here and the second one is the NAND SR latch now this is a kind of disadvantage because every time you need to know about the internal circuit whether someone is using the nor SR latch or an and SR a Ledge
now as the name says it latches 0 or 1 like your door latches it latches 0 or 1 in this circuit but there's a difference in latching your door and the latching of data is 0 or 1 in this circuit in case of door when you latch it whatever inside the room cannot get out it is stored inside and also anything from outside cannot come in but in this case if I change this input SN are definitely the store data will get changed and this SN R may change accidentally or intentionally because we use this
circuit along with different circuits and if R and s is connected to some output then if that output changes this SN R will also change and the store data will be removed this is the disadvantage and we can overcome it by using the clock by using the clock I will explain clock in great detail in the next presentation and after this you will know the use of clock in controlling this store well you so why I am calling this inputs s and R because this R stands for the reset and this S stands for D
set in digital electronics if I say reset it means the output is equal to 0 we have reset it our circuit and in that case outward will be 0 and if I say set it means output is equal to 1 so this input this input if equal to 1 will make output Q equal to 1 and if this input is equal to 1 it will make the output Q equal to 0 because of this we call it reset and set and R represent recent as represent set and we will definitely prove it and for that
I need the truth table of the nor gate I am using nor gate here so I need the truth table for the nor gate so let's make one let's say the two inputs are a and B the output is y I am using two input nor gate so I have four possible combinations and you definitely know the output depending upon these combinations it is 1 0 0 or 0 so this is the truth table for two input nor gate for two input nor gate and we will use this truth table in our analysis I am
going to analyze this circuit for different cases and let's have our first case the case number 1 and in this case I will make s equal to 0 R equal to 1 so s is 0 R is 1 and now we are interested in finding out our outputs Q and Q complement I have already written this output complement of this one because they are always complement and you can definitely prove it so let's start with it when s is 0 and R is 1 from this table you can see if any input if any input
is 1 the output is going to be 0 and we don't have to see the other input beam zero and one but output is always zero because of a equal to 1 and 1 so R is equal to 1 so this will make Q equal to 0 and I have already explained you the reset input will reset the circuit and Q is equal to 0 now Q is connected to the input of this nor gate so this 0 will reflect here and we have 0 0 as the 2 input for this nor gate and when
the two inputs are 0 it will give us output as 1 so Q complement is equal to 1 and you can see that they are complement to each other so let me write this down Q is equal to 0 and Q complement is equal to a 1 now I have told you that we want to store the data and by storing I mean if I remove this input R equal to 1 s equal to 0 if I remove this input the data must be stored the output must not change and remain 0 and 1 let's
try to find this out whether it works like this or not I will make s equal to 0 R equal to 0 I have removed the inputs and now we will again find out Q and Q complement so let's see what happens in that case Q complement is 1 and it is connected to this nor gate so we have 1 here this R is now 0 so we have 0 1 and when 0 1 is there the output is going to be 0 so Q is equal to 0 so Q is equal to 0 this
Q is connected here so 0 0 will give us 1 0 0 will give us 1 so Q complement is also equal to 1 so you can clearly see that we have stored the datums I have removed the inputs I have removed s and R I have made them 0 0 but we have output equal to 0 1 which is same as the previous case so we call we call this condition memory because the output or the stored data remains the same so when s is 0 R is 0 we have the memory we have
the previous output now let's move to the case number two to the case number two and in this I will make s equal to 1 R equal to 0 and we will find out Q and Q complement ok I will rub this down and we will do the analysis for the second case ok and s is 1 so s is 1 R is 0 and I have already told you if any input is 1 we don't have to see for the other input the output is going to be 0 here s is 1 so Q
complement will be equal to 0 and this Q complement is connected here so we have 0 here 0 0 will give us 1 0 0 will give us 1 so now we have Q as 1 and Q complement as 0 and you can see when s is equal to 1 when set input is equal to 1 the output is equal to 1 so this is justifying what I have explained you earlier now again we will remove the input I will make s equal to 0 R equal to 0 and we will find out Q and
Q complement okay if you know this thing if you understand this thing then definitely you're not going to face any problem in the sequential circuit this is the most important point in the sequential circuit you have to understand this latch you can easily understand your flip-flop you can easily understand your counters registers etc and you will definitely score a good marks so this is a very important presentation and I am explaining everything in a great detail so please pay attention and if possible write these things down so let's move to our circuit now Q in
last case is equal to 1 Q is equal to 1 so here I have 1 this S is now 0 so 1 0 you can see will give me 0 so Q complement is 0 this Q complement is connected here and we have 0 0 so Q is equal to 1 now again you can see again you can see if s is equal to 0 our is equal to zero we have the previous outputs Q was one again we have Q equal to 1 Q complement was zero and in this case also Q complement is
equal to zero so I have proved twice that s equal to 0 and R equal to zero gives us the memory state we are storing the previous values and s equal to 0 R equal to 1 is giving me Q equal to 0 Q complement equal to 1 s equal to 1 R equal to 0 gives me Q equal to 1 Q complement equal to 0 so these are the two very important cases in SR latch using the nor gate but there is one most important case still left and this is the most important point
in this whole lecture so let's move to case number 3 I have made s equal to 0 R equal to 1 s equal to 1 R equal to 0 but what if I make s equal to 1 and also R equal to 1 this is very important and very confusing at the same time so let me up this zeros and 1 that I have used for the previous analysis and now we will analyze case number 3 when s is equal to 1 and R is equal to 1 we will find out Q and Q complement
as is 1 R is a 1 and from this truth table you can see when we have input as 1 the output is going to be 0 so R is 1 this makes Q equal to 0 s is 1 this makes Q complement equal to 0 so there is a contradiction the two outputs are same Q is equal to Q complement which is definitely not true they must be complement of each other and thus thus I can say that as equal to 1 and R equal to 1 is not used there is something wrong about
this configuration but this is not the only problem that Q is equal to Q complement if I make s equal to 0 and R equal to 0 let's see what we have in that case and this is really disturbing the thing you are going to see now will disturb you so be prepared for it let's make our equal to 0 s equal to 0 I have removed the input and let's start our analysis with Q q is equal to 0 so we have 0 here 0 0 will give me 0 0 will give me 1
so Q complement is 1 Q complement is 1 and when Q complement is 1 definitely I have second input as 1 0 1 will give me 0 so Q is equal to 0 simple till now everything is fine Q is 0 Q complement is 1 definitely it is not storing the previous output I had started my analysis with Q okay what if I start my analysis with Q complement let's see Q complement first forget these things okay and let's start with Q complement r is 0 s is 0 when Q complement is 0 we have
0 0 for this nor gate and 0 0 will give us 1 so Q is equal to 1 this Q is connected here so we have 1 0 & 1 0 will give me 0 now Q is 1 now Q is 1 and Q complement is equal to 0 so for the same configuration when s is equal to 0 r is equal to 0 we have different output and this is definitely not good thing to have q is equal to 0 Q complement is equal to 1 and then again we have Q equal to 1
Q complement equal to 0 so this is a really not good thing to have in our SR latch so a very important thing comes here this case number 3 is not used we don't use s equal to 1 and R equal to 1 for s our latch and you will definitely not use it in SR flip-flop because it will yield two conditions which is not acceptable the first one Q is equal to Q complement and if you make s equal to 0 R equal to 0 you want to store them because whenever you want to
store the data you just remove the input as equal to 0 and R equal to 0 and you have the previous data is stored in your latch but here in this case you can see we are having the output depending upon our observation if I seek you fast I have different output if I seek you compliment first I have different output so we do not use s equal to 1 R equal to 1 in s our allege now you can make a table and you can summarize the whole thing in that you can write s
and R they are your inputs you have to output Q Q compliment and if s is 0 R is 0 you can see you have a memory you have a memory or you can say that as before whatever the value stored earlier is going to be the same and when s is 0 R is 1 from this case you can see when s is 0 R is 1 Q is equal to 0 Q complement is equal to 1 and when s is 1 R is 0 from case number 2 you can see this is 1
R is 0 will give us Q equal to 1 Q complement equal to 0 so 1 0 and the last case when s is 1 R is 1 we don't use it so i will write not used and I have given the reason why we don't use it I hope you got this reason if you have any doubt you can ask in the comment section now we can move to the nand SR latch and I'm not going to explain everything because you can do it by yourself but I will definitely make the circuit and the
table for this I will use a NAND gate instead of the nor gate in this circuit I used the nor gates but now I will use the NAND gate and the remaining thing will be same only there is one more change that I will tell you the change is in the input we have set and reset in this case we had a reset and set so this is a small change that you have to make in the NAND SR latch the output is q q complement so let's make the table for this circuit you can
definitely prove it like this you have to follow the same steps first you have to make the 2 table for the NAND gate and then follow all the steps that we have done in this presentation and we have s our cue cue complement zero zero remember in this case when 0 0 is the value for set and reset we have not used a state where as in this case when s was one R was one we had not used state here things will get reversed when s is 0 R is 1 we have Q as
1 Q complement as 0 when s is 1 R is 0 we have qa0q complement is 1 and when 1 a 1 this is the memory state this is the memory state so if you want to store your data you have to make s equal to 1 R equal to 1 then only your data will be stored and if you make s equal to 0 R equal to 0 it is not used state the confusion like this will again arise so this is all for this presentation please go and ask if you have any doubt
in this because it is very very important presentation and if you understand it right now you will not face any problem in the coming presentations so this is all see you in the next presentation
